image quality of smartphones will exceed SLRs in a few years

From Sony Terushi Shimizu

before:

new: 2-layered transistor pixel:

  Because pixel transistors other than transfer gates (TRG), including reset transistors (RST), select transistors (SEL) and amp transistors (AMP), occupy a photodiode-free layer, the amp transistors can be increased in size.

 This will double the saturation signal level (Full well capacity), QE, widen dynamic range and noise reduction available from this new technology will prevent underexposure and overexposure in settings with a combination of bright and dim illumination (e.g., backlit settings) and enable high-quality, low-noise images even in low-light (e.g., indoor, nighttime) settings.’ 

 

From an engineering and manufacturing perspective, the 2-Layer Transistor Pixel design requires nanometer-level precision for arranging the photodiodes and pixel transistors. Sony adopted a 3D sequential integration process instead of conventional bonding of completed wafers. After the photodiode is formed, two layers are bonded together and then the photodiode is used to line up the creation of the transistor in the second layer. As Nakazawa puts it, alignment accuracy is determined by the lithography rather than the bonding.

The process includes its own challenges, including heat in the production process after stacking the wafers. Whereas traditional CMOS sensor production requires heat resistance of around 400° C, the new design requires a much higher heat resistance of over 1,000° C. To address the problem, Sony developed new bonding technology and built its transistors to adapt.

Edge AI computing, and multi frame processing to improve speed of image processing 

ToF and Lidar to provide sensor to object distance information 

8k HDR video made possible in mobile imaging

Blurring and lighting control via multi exposures and multi focus stacking 

challenges:

The primary challenge in fabricating the PPD ( pinned photodiode) is achieving both good Full well capacity and complete charge transfer. The challenge increases with reduced operating voltages and smaller pixel size. Secondary challenges include reducing leakage and dark current from the transfer gate, and decreasing charge transfer times.

 

some questions:

pixel size (1um?), FWC ( 12k e-?) and QE ( +19%?) 

how this tackles image lag, dark current, crosstalk?

how about the transfer gate connection to Amp transistor? according the SEM photo of the sensor, the RST is on top of photodiode (PD), whereas TRG is at the bottom. The interconnection path is still occupying part of the horizontal spacings( not shown) and will limit the aperture size.

readout noise is exponentially proportional to readout frequency. How to tackle readout noise in 8k video?

Nikkei

Amateurphotographer. 

Petapixel

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