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  RK3588-EVB开发板的camera配置来进行说明;RK3588 的camera通路,下图是RK3588 camera连接链路示意图，可以支持7路camera。 rk3588支持两个dcphy，节点名称分别为csi2_dcphy0/csi2_dcphy1。每个dcphy硬件支持RX/TX同时使用，对于camera输入使用的是RX。支持DPHY/CPHY协议复用；需要注意的是同一个dcphy的TX/RX只能同时使用DPHY或同时使用CPHY。其他dcphy参数请查阅rk3588数据手册。 rk3588支持2个dphy硬件，这里我们称之为dphy0_hw/dphy1_hw，两个dphy硬件都可以工作在full mode 和split mode两种模式下。 dphy0_hw: full mode：节点名称使用csi2_dphy0，最多支持4 lane。 split mode： 拆分成2个phy使用，分别为csi2_dphy1（使用0/1 lane）、csi2_dphy2(使用2/3 lane)，每个phy最多支持2 lane。 当dphy0_hw使用full mode时，链路需要按照csi2_dphy1这条链路来配置，但是节点名称csi2_dphy1需要修改为csi2_dphy0，软件上是通过phy的序号来区分phy使用的模式。 dphy1_hw: full mode：节点名称使用csi2_dphy3，最多支持4 lane。 split mode： 拆分成2个phy使用，分别为csi2_dphy4（使用0/1 lane）、csi2_dphy5(使用2/3 lane)，每个phy最多支持2 lane。 当dphy1_hw使用full mode时，链路需要按照csi2_dphy4这条链路来配置，但是节点名称csi2_dphy4需要修改为csi2_dphy3，软件上是通过phy的序号来区分phy使用的模式。 使用上述mipi phy节点，需要把对应的物理节点配置上。 （csi2_dcphy0_hw/csi2_dcphy1_hw/csi2_dphy0_hw/csi2_dphy1_hw） 每个mipi phy都需要一个csi2模块来解析mipi协议，节点名称分别为mipi0_csi2~mipi5_csi2。 rk3588所有camera数据都需要通过vicap，再链...

 From circuit valley  , which is one big step forward from previous dev kit format to now industrial c mount enclosure. main ICs are: camera sensor: IMX290, IMX327 or IMX462 FPGA: Lattice CrossLink-NX LIFCL-40 (4-lane MIPI D-PHY transceivers at 10 Gbps per PHY / 2.5 Gbps per lane), USD60 RAM: 2x 16Mybte RAM, USD 50 USB controller:  CYUSB3014 so this FPGA should be able to drive four IMX462 at almost full bitrates blog github CrossLink-NX eval board (USD130) CrossLink NX LIFCL-VIP-SI-EVN , four IMX258 cam  input Driving Imx219 by lattice  FPGA .  Imaginghub .  SpartanEdge

Zynq-7000 is the most integrated low cost one-chip-for-all solution at this moment, it can be used for interfacing with camera sensors. however, from Igor Gorokhov of Aldec: Although the Zynq-7000 devices are not fully electrically compatible with the MIPI D-PHY physical protocol used for CSI-2, those data lines can be accessed by Zynq using the LVDS I/O standard running in HS mode. Adam Taylor's blog , on using Micro Zed board: When we implement a MIPI CSI-2 solution in our FPGA, we will most often be using a D-PHY based solution. Even if a IP core is used for the higher levels of the protocol, the D-PHY is normally configured by the developer as that is where the line rate, clocking and pin out are defined. This D-PHY block is then connected to the MIPI IP Core. Depending upon if we are implementing the MIPI solution in a Zynq (or seven series FPGA) or a Zynq MPSoC (UltraScale+ FPGA), the physical elements of the D-PHY will be different. T...

dart camera module from Basler sensor: AR0521 5 Megapixel This Driver Package includes the ISP logic, which now implements former camera firmware functionality on the Snapdragons Spectra™ ISP. The Driver Package also implements the interface to the pylon Camera Software Suite and thus provides the same level of convenience as for any non-embedded camera interface (e.g., USB 3.0, GigE). seems to need some time to integrate to raspberry Pi Basler 

those image sensors for webcam applications are highly integrated, and can be connected to PC via USB, eg OV7725 vga Sony image sensor interface is using sub-LVDS, sort of bridge circuitry is required to convert to MIPI CSI protocol sensor bridge: Lattice   various solutions, eg  MachXO3    ,$25 Lattice FPGA Mach project IMX219 running on 4 lanes with MachXO3 Xilinx Virtex(very high performance), Zynq(64 bit controller + FPGA) Xilinx appnote Epson S2D13P04 ( details to be added ) btw, HiSense 3516 series are image sensor SoC which encodes videos in H.264 , H.265 formats, not really intended for raw image or videos System level: Cypress EZ-USB CX3, with USB3 interface video intro Denebola development kit from E-Con : eCon e-CAM130_CUTK1 connecting to a Tegra K1 board via 4-lane MIPI CSI-2 interface: Texas Instruments DaVinci imaging processor with Lattice sensor bridge: Raspberry Pi ...