Zynq-7000 is the most integrated low cost one-chip-for-all solution at this moment, it can be used for interfacing with camera sensors.
however, from Igor Gorokhov of Aldec:
Although the Zynq-7000 devices are not fully electrically compatible with the MIPI D-PHY physical protocol used for CSI-2, those data lines can be accessed by Zynq using the LVDS I/O standard running in HS mode.
Adam Taylor's blog, on using Micro Zed board:
When we
implement a MIPI CSI-2 solution in our FPGA, we will most often be
using a D-PHY based solution. Even if a IP core is used for the higher
levels of the protocol, the D-PHY is normally configured by the developer
as that is where the line rate, clocking and pin out are defined. This
D-PHY block is then connected to the MIPI IP Core.
Depending
upon if we are implementing the MIPI solution in a Zynq (or seven
series FPGA) or a Zynq MPSoC (UltraScale+ FPGA), the physical elements
of the D-PHY will be different.
The
MPSoC includes D-PHY support directly within the IO resources. However,
the Zynq does not as such we have two options for the Zynq depending
upon the data rate.
.....We can implement an external resistor-based solution which implements a D-PHY compatible solution. Alternatively, we can use an external PHY such as the Meticom's MC20002.
From Zynqberry:
MIPI CSI2 camera processing path is bit longer, it is first converted from CSI2 signals into intermediate PPI Interface also defined by MIPI alliance as the MIPI PHY interface. PPI is then converted to AXI4-Stream. As next step the video data passes dual clock FIFO to move into system clock domain. Then the camera data is processed to convert RAW10 format into RGB. Before going to Xilinx VDMA IP Core the video data is resized so that it can directly be displayed on HDMI monitor.
Adam Taylor's blog on zynqberry
bear in mind of all such limitations, zynq is still a versatile platform as long as the data rates are below the reduced speed D-PHY, Here is a demo based on ZYBO Z7 board , using PCAM-5C ( 5MP OV5640) camera
More details on
The resistor network for transforming an LVDS receiver into a compatible D-PHY receiver , in XAPP894
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