sub micron pixel

Higher-resolution cameras don’t necessarily equate to better photos. “It’s a tradeoff question between the pixel size and resolution,” Girardin said. “Pixel scaling means that it has more pixels. When the resolution is more than 40MP and 50MP, the capabilities may be beyond the human eye to see what they capture. For CMOS image sensors, the pixel with a better quantum efficiency (QE) and a signal-to-noise ratio are the most important things for image quality.”

pixel scaling ( from microns to sub microns pixel pitch), new technology breakthrough must be introduced

challenges:
pixel crosstalk
diffraction
low light sensitivity

Technology enablers

to make a taller photodiode ( thicker active Si layer) , DTI ( Deep Trench Isolation)
VTG (Vertical Transfer Gate)
buried CFA
usually realised as Back side Illumination (BSI) configuration
narrow metal grids for crosstalk suppression
narrow dielectric wall for Quantum Efficiency improvement

new process:
high-k passivation films

new die-stacking and interconnects:
Triple die stack ( CIS + ISP + DRAM )

benefits:
higher spatial resolutions
higher color fidelity

adaptive digital pixel binning

ncbi pmc gov

sharpcap forum

Sony IMX650 sensor in Huawei P30 Pro, low light test

some astrophotos

comet Neowise C2020 F3 from bbyaya george chan(IMX650), handheld:

from Lu Tai Nin, Huawei P20 Pro (IMX600) with tripod:

13 July 2021, from Sony marketing on mobile ccd sensor evolution:

"The evolution of CMOS image sensors and the prospects utilizing advanced imaging technologies promise to improve our quality of life. CMOS image sensors now dominate the market of digital cameras with the advent of parallel ADCs and back-illuminated technology. Moreover stacked CMOS image sensors continue to enhance functionality and user experience in mobile devices.

We introduce the evolution of image sensor architecture for accelerating drastic performance improvements and for integrating edge computing connected to the sensor layer through stacking technologies. Furthermore, the fine pitch connection between the pixel and logic layers makes pixel parallel circuit architecture practical for the next stage of evolution."